Cardinality and Invariant Subspaces by L. de Branges

By L. de Branges

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As digital signal processing-intensive applications increasingly move into the mainstream of computing and electronics products, general-purpose processors have begun to adopt some of the features of DSP processors to make them more suitable for DSP-intensive applications. For example, the Motorola/IBM PowerPC 601, the MIPS RIOOOO, the Sun UltraSPARC, and the Hewlett-Packard PA-7100LC general-purpose microprocessors are all able to perform a floatingpoint multiply-accumulate in one instruction cycle under certain circumstances.

Floating-point representations used in DSP processors, while somewhat longer and more elaborate than this example, are similar in structure. Note that the Implied mantissa bit is always assumed to be 1, and therefore Is never actually explicitly stored. 0. This guarantees that the precision of any floating-point value is no less than half of the maximum available precision. Thus, floating-point processors maintain very good precision with no extra effort on the part of the programmer. In practice, floating-point DSPs generally use a 32-bit format with a 24-bit mantissa and one implied integer bit, providing 25 bits of precision.

However, support for scaling the multiplier result in lieu of guard bits is sufficient for many applications. A few processors, such as the Texas Instruments TMS320Clx, lack both guard bits and the ability to efficiently scale the product register. This requires the multiplier input to be scaled to avoid overflow, which can result in significantly reduced precision. The lack of both accumulator guard bits and support for scaling the product register is a serious limitation in many situations. ALU DSP processor arithmetic logic units implement basic arithmetic and logical operations in a single instruction cycle.

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