By Steve Leibson
Microprocessor cores used for SOC layout are the direct descendents of Intel's unique 4004 microprocessor. simply as packaged microprocessor ICs fluctuate generally of their attributes, so do microprocessors packaged as IP cores. even though, SOC designers nonetheless examine and choose processor cores the way in which they formerly in comparison and chosen packaged microprocessor ICs. the massive challenge with this feature process is that it assumes that the legislation of the microprocessor universe have remained unchanged for many years. This assumption is not any longer valid.
Processor cores for SOC designs could be way more plastic than microprocessor ICs for board-level method designs. Shaping those cores for particular purposes produces far better processor potency and lots more and plenty decrease method clock premiums. jointly, Tensilica's Xtensa and Diamond processor cores represent a kinfolk of software-compatible microprocessors protecting an incredibly extensive functionality variety from uncomplicated regulate processors, to DSPs, to 3-way superscalar processors. but all of those processors use an identical software-development instruments in order that programmers accustomed to one processor within the family members can simply change to another.
This ebook emphasizes a processor-centric MPSOC (multiple-processor SOC) layout kind formed through the realities of the 21st-century and nanometer silicon. It advocates the task of projects to firmware-controlled processors every time attainable to maximise SOC flexibility, minimize energy dissipation, lessen the dimensions and variety of hand-built common sense blocks, scale back the linked verification attempt, and reduce the final layout chance.
· a necessary, no-nonsense advisor to the layout of 21st-century mega-gate SOCs utilizing nanometer silicon.
· Discusses cutting-edge key matters affecting SOC layout, according to author's many years of private event in constructing huge electronic structures as a layout engineer whereas operating at Hewlett-Packard's computer machine department and at EDA computing device pioneer Cadnetix, and protecting such issues as an award-winning expertise journalist and editor-in-chief for EDN journal and the Microprocessor Report.
· Explores conventionally approved obstacles and perceived limits of processor-based method layout after which explodes those synthetic constraints via a clean outlook on and dialogue of the precise skills of processor cores designed in particular for SOC design.
· Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC layout with a glance at the place the has come from, and the place it truly is going.
· Easy-to-understand factors of the services of configurable and extensible processor cores via a close exam of Tensilica's configurable, extensible Xtensa processor middle and 6 pre-configured Diamond cores.
· the main entire overview to be had of the sensible elements of configuring and utilizing a number of processor cores to accomplish very tricky and bold SOC cost, functionality, and gear layout targets.
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Extra resources for Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores
4 shows a 2-processor system with a shared DMA controller, a shared-memory controller, and a collection of peripheral blocks. Study the block diagram alone and you will not discern the OMAP chip's intended function. The OMAP chip's system design doesn't at all resemble the actual application problem's block diagram. 3 This generic, microprocessor-based system is representative of many system designs. It is so successful because of the microprocessor's inherent flexibility, not because this system-design matches the actual needs of a system.
Peripheral LogicBlock I >. 14 System design using wires between computational elements. should have been involved in the process all along the way--during model development, abstract system simulation, selection of communication mechanisms, and during processor selection and ASIP development. The software team's participation during these design steps will be a major factor that determines the success of the design project. At the same time, the hardware team now has a set of hardware blocks to integrate.
This inflexibility elevates design risk because an SOC that incorporates such blocks must be redesigned to accommodate any design changes brought on by bugs, specification changes, or other market forces. It is possible to boost a microprocessor's performance for specific applications by adding execution resources directly to the processor's ISA. This is the underlying premise behind the development of configurable processor cores or ASIPs. ISA extension is not new. Processor vendors have long added ISA extensions to enhance application performance.