EDA for IC System Design, Verification, and Testing by Louis Scheffer, Luciano Lavagno, Grant Martin

By Louis Scheffer, Luciano Lavagno, Grant Martin

Offering a complete evaluate of the layout automation algorithms, instruments, and methodologies used to layout built-in circuits, the Electronic layout Automation for built-in Circuits Handbook comes in volumes. the 1st quantity, EDA for IC approach layout, Verification, and Testing, completely examines system-level layout, microarchitectural layout, logical verification, and trying out. Chapters contributed by way of top specialists authoritatively talk about processor modeling and layout instruments, utilizing functionality metrics to choose microprocessor cores for IC designs, layout and verification languages, electronic simulation, acceleration and emulation, and masses extra. retailer at the whole set.

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Extra info for EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Hdbk)

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Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods, McGraw-Hill, New York, 1995. [15] J. Elliott, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design, Kluwer Academic Publishers, Dordrecht, 2000. [16] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, McGraw-Hill, New York, 1994. [17] G. DeMicheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, 1994. [18] I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Defining Fast CMOS Circuits, Academic Press, New York, 1999.

Another way to tackle the large number of simulation vectors during system verification is through emulation or hardware acceleration. These techniques use specially configured hardware to run the simulation. In the case of hardware acceleration, the company can purchase special-purpose hardware, while in the case of emulation the verification engineer uses specially configured FPGA technology. In both cases, the system verification engineer must synthesize the design and testbench down to a gate-level model.

Cheng, Formal Equivalence Checking and Design Debugging, Kluwer Academic Publishers, Dordrecht, 1998. [13] R. Baker, H. Li, and D Boyce, CMOS Circuit Design, Layout, and Simulation, Series on Microelectronic Systems, IEEE Press, New York, 1998. [14] L. Pillage, R. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods, McGraw-Hill, New York, 1995. [15] J. Elliott, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design, Kluwer Academic Publishers, Dordrecht, 2000.

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