Embedded Memory Design for Multi-Core and Systems on Chip by Baker Mohammad

By Baker Mohammad

This e-book describes a few of the tradeoffs platforms designers face while designing embedded reminiscence. Readers designing multi-core structures and structures on chip will enjoy the dialogue of other issues from reminiscence structure, array association, circuit layout strategies and layout for try out. The presentation permits a multi-disciplinary method of chip layout, which bridges the distance among the structure point and circuit point, as a way to tackle yield, reliability and power-related matters for embedded reminiscence.

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The SRAM arrays contain more than 90 % of the device and use 50 % of the chip area. Tag array itself consumes more than half the power of the memory subsystems. Hence, early planning and thorough understanding of all the factors that contribute to the power, area, and speed in SRAM memory access is also essential to making the right tag selection. 1 Memory Size, Access Time, and Power Relationships As was shown in Chap. 2 there are many levels of embedded memory and caches. The reason for splitting into multiple levels is to tradeoff between speed and capacity [34, 51].

From a physical design point of view it means adding at least 2-bits per cache line to indicate the state it is in. This has normally become part of the state array of the cache subsystem. 1 SRAM Cell and Array Design The SRAM 6T cell typically is the most frequently used cell in designs requiring on-chip memory due to its fast access time and relatively small area. Its main function is to store data for the program to access; it retains the stored data so long as power is applied (volatile). 1.

The hit cost is determined based on the circuit design of the memory and depends on the cell type, size of the subarray and on the overall memory size. 3 Memory Hierarchy for Multi-core General Purpose Processor and SOC 31 From example above design 2 with smaller memory size has better performance than design 1 or design 3. The same calculation can be used to analyze memory size and energy cost. 3 Memory Hierarchy for Multi-core General Purpose Processor and SOC Embedded memory hierarchy and implementation differs between high-end general purpose microprocessors with multi-core chip like the IBM server chip Figs.

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