Energy Efficient Microprocessor Design by Thomas D. Burd

By Thomas D. Burd

This paintings begun in 1995 as an outgrowth of the InfoPad venture which confirmed us that during order to minimize the power intake of a transportable multimedia terminal that anything needed to be performed concerning the intake of the microprocessor subsystem. The layout of the InfoPad tried to lessen the necessities of this normal pur­ pose processor by means of relocating the computation into the community or by way of hugely optimized built-in circuits, yet despite those efforts it nonetheless used to be an incredible customer of strength. the explanations for this grew to become obvious as we made up our minds that the strength required to accomplish a functionality in committed can be numerous orders of value under that ate up within the InfoPad microprocessor. We as a result set out on an entire fledged assault on all points of the microprocessor strength intake [1 J. After enormous research it grew to become transparent that notwithstanding larger circuit layout and a circulation­ coated structure might help in our objective of strength relief, that the largest profits have been to be came across by means of working at lowered voltages. For the busses and VO this may be complete with out major degradation of the processor functionality, yet this was once no longer an easy resolution whilst utilized to the middle of the processor sub­ method (CPU and memory).

Show description

Read or Download Energy Efficient Microprocessor Design PDF

Best microprocessors & system design books

Microprocessor Design: A Practical Guide from Design Planning to Manufacturing

This specific step by step consultant is a whole advent to fashionable microprocessor layout, defined in basic nontechnical language with no advanced arithmetic. a fantastic primer for these operating in or learning the semiconductor undefined, Microprocessor layout explains all of the key recommendations, phrases, and acronyms had to comprehend the stairs required to layout and manufacture a microprocessor.

Logic Synthesis Using Synopsys®

Common sense Synthesis utilizing Synopsys®, moment variation is for somebody who hates analyzing manuals yet could nonetheless prefer to research good judgment synthesis as practised within the genuine international. Synopsys layout Compiler, the top synthesis device within the EDA market, is the first concentration of the ebook. The contents of this publication are especially prepared to aid designers conversant in schematic capture-based layout to advance the necessary services to successfully use the Synopsys layout Compiler.

Computational Intelligence: Methods and Techniques

This booklet specializes in a variety of recommendations of computational intelligence, either unmarried ones and people which shape hybrid equipment. these suggestions are this day ordinarily utilized problems with synthetic intelligence, e. g. to procedure speech and traditional language, construct specialist platforms and robots. the 1st a part of the e-book provides tools of information illustration utilizing diversified thoughts, specifically the tough units, type-1 fuzzy units and type-2 fuzzy units.

Time-Triggered Communication

Time-Triggered communique is helping readers construct an knowing of the conceptual origin, operation, and alertness of time-triggered communique, that is well-known for embedded structures in a various variety of industries. This e-book assembles contributions from specialists that learn the variations and commonalities of the main major protocols together with: TTP, FlexRay, TTEthernet, SAFEbus, TTCAN, and LIN.

Extra resources for Energy Efficient Microprocessor Design

Example text

20}. A more practical limit is ~IOOmV above max(VTp,VTn ), to provide an operating margin for preventing the MOSFET's from entering this region. G '0 ! 2 IO . .. .. . -r-------------. : • -. 17 VDD , VT, and Range of Energy Consumption vs. Process Technology. The upper bound on voltage is detennined by gate-oxide breakdown [2. 13}. 3V. 3V. While the MOSFET's can be operated at a higher voltage, it is generally not recommended for long-term gateoxide reliability. As process technology advances, the reduction in gate-oxide thickness necessitates a reduction in the rated maximum supply voltage.

1994. 2} A. Chandrakasan, S. W. Brodersen, "Low-Power CMOS Digital Design", IEEE Journal of Solid State Circuits, Apr. 1992, pp. 47384. A. w. Brodersen, Low-power Digital CMOS Design, Kluwer Academic Publishers, Boston, 1995. M. 15} 42 Proceedings of the Thirty-Ninth IEEE Computer Society International Conference, Mar. 1994, pp. 144-7. T. Ikeda, "ThinkPad Low-Power Evolution", Proceedings of the IEEE Symposium on Low Power Electronics, Oct. 1995, pp. 6-7. A. Chandrakasan, A. W. Brodersen, "A Low Power Chipset for Portable Multimedia Applications", IEEE Journal of Solid State Circuits, Vol.

E. 14) The critical path delay can be related back to the previous delay model by summing up the delay over all M gates in the critical path: Critical Path Delay:: ~D M ~ CLi 2 . L... e. number of gates), and average values for CL and Ware used. 16) Typical units for opemtions per clock cycle are MIPSlMhz, and SPECint95/MHz when opemtions are respectively defined as instructions and benchmark progmms. 3 Energy Use Metrics While the energy consumed per operation should always be minimized, no single metric quantifies the efficiency of energy use for all digital systems, since the metric must be dependent on the system's throughput constmints.

Download PDF sample

Rated 4.29 of 5 – based on 9 votes