Heterogeneous Multicore Processor Technologies for Embedded by Kunio Uchiyama

By Kunio Uchiyama

To fulfill the better standards of digitally converged embedded platforms, this booklet describes heterogeneous multicore know-how that makes use of several types of low-power embedded processor cores on a unmarried chip. With this expertise, heterogeneous parallelism might be carried out on an SoC, and bigger flexibility and more desirable functionality in keeping with watt can then be completed. This booklet defines the heterogeneous multicore structure and explains intimately a number of embedded processor cores together with CPU cores and special-purpose processor cores that in achieving hugely arithmetic-level parallelism. The authors built 3 multicore chips (called RP-1, RP-2, and RP-X) based on the outlined structure with the brought processor cores. The chip implementations, software program environments, and functions operating at the chips also are defined within the book.

  • Provides readers an outline and useful dialogue of heterogeneous multicore applied sciences from either a and software program element of view;
  • Discusses a brand new, high-performance and effort effective method of designing SoCs for digitally converged, embedded systems;
  • Covers matters resembling structure and chip implementation, in addition to software program concerns akin to compilers, working structures, and alertness programs;
  • Describes 3 chips constructed in keeping with the outlined heterogeneous multicore structure, together with chip implementations, software program environments, and dealing applications.

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The cache sizes are 8 and 16 KB. 5 Zero-Cycle Data Transfer Since the number of transfer instructions of an SH-4 program was more than that of the other architecture, the transfer instructions were categorized to BO group. Then the transfer instructions can be inserted to any unused issue slots. Further, a zerocycle transfer operation was implemented for the transfer instructions and contributes to reduce the hazard. The result of the transfer instruction already exists at the beginning of the operation as an immediate value in an instruction code, a value in a source operand resister, or a value on the fly in a pipeline, and it is provided to the pipeline at the ID stage, and the value is just forwarded in the pipeline to the WB stage.

An out-of-order issue was the popular method used by a high-end processor in order to enhance the cycle performance. However, it required much hardware and was too inefficient especially for general-purpose register handling. The SH-X adopted an in-order issue except some branches using no general-purpose register. The branch penalty was the serious problem for the superpipeline architecture. In addition to the method of the SH-4, the SH-X adopted a branch prediction and an out-of-order branch issue, but did not adopt a more expensive way with a BTB and an incompatible way with plural instructions.

It also lengthens the decoding stages into two except for the address calculation and relaxes the decoding time. With the conventional architecture shown in Fig. 1 Embedded CPU Cores 35 Load: MOV. L @R0, R1 ID E1 E2 E3 R1, R2 ALU: ADD ID E1 E2 E3 Conventional Architecture: 2-cycle Stalls Load: MOV. L @R0, R1 ID E1 E2 E3 R1, R2 ALU: ADD ID E1 E2 E3 Delayed Execution: 1-cycle Stall Fig. 8 Load-use conflict reduction by delayed execution stages, and the load data is available at the end of the E3 stage.

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