High performance memory testing: design principles, fault by R. Dean Adams

By R. Dean Adams

Are reminiscence functions extra severe than they've been long ago? convinced, yet much more serious is the variety of designs and the sheer variety of bits on each one layout. it's guaranteed that catastrophes, that have been refrained from some time past simply because stories have been small, will simply happen if the layout and try out engineers don't do their jobs very conscientiously.
High functionality reminiscence checking out: layout ideas, Fault Modeling and Self Test relies at the author's two decades of expertise in reminiscence layout, reminiscence reliability improvement and reminiscence self try out.

High functionality reminiscence trying out: layout rules, Fault Modeling and Self Test is written for the pro and the researcher to assist them comprehend the thoughts which are being demonstrated.

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Extra info for High performance memory testing: design principles, fault modeling, and self-test

Sample text

There can be numerous things going on “in the back of our minds” and there are automatic functions such 48 Chapter 3 as breathing, circulation, and so on that are maintained while our mind is occupied elsewhere. A multi-port memory allows two “cognitive” exercises to be performed simultaneously. It is like having two people looking at two different books in one library at the same time. The library provides multiport operation. The challenge comes when two people want to use the same book at the same time.

The relentless press of Moore’s law drives more and more bits onto a single chip. The large number of bits means that methods that were “gotten away with” in the past will no longer be sufficient. Because the number of bits is so large, fine nuances of fails that were rarely seen previously now will happen regularly on most chips. These subtle fails must be caught or else quality will suffer severely. Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design.

For this circuit the bit-line differential is applied to the drains of the four transistors forming the sense amplifier’s latch. An alternative is to have a latch type sense amplifier where the differential signal is applied to the gates of the NFETs from the sense amplifier latch as shown in Figure 2-15. When this configuration is used a different bit line isolation circuit may be employed. Another alternative to the latch type sense amplifier is to remove the PFETs from Figure 2-14 [15]. When this circuit arrangement is used, the isolation circuit keeps the bit lines attached to the sense circuit and the bit lines hold the high node in an elevated state while the low node is actively pulled down by the sense amplifier.

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