By Anupam Chattopadhyay, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
Increasing complexity of contemporary embedded structures calls for procedure designers to ramp up their layout productiveness with no compromising functionality targets. this can be promoted through sleek digital method point (ESL) options. Language-driven Exploration and Implementation of partly Re-configurable ASIPs addresses an immense phase of the ESL sector via modeling in part re-configurable processors through high-level structure Description Language (ADL). This method additionally tricks an forthcoming evolution within the sector of re-configurable process layout.
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Additional info for Language-driven Exploration and Implementation of Partially Re-configurable ASIPs
More recently, a heuristic algorithm with polynomial-time complexity is reported by . In this heuristic, a MIMO DFG pattern is identified within a basic block. The computational complexity of this heuristic is reported to be O(N I +O ), where I and O are the cardinality of the input and output sets respectively. In an interesting development of these approaches, an Integer Linear Programming (ILP) formulation is presented for the first time by . Using this ILP formulation, it is shown that, the runtime is much better than the previously presented heuristics.
Stretch’s S5000 family of software programmable processors consist of the 32-bit Xtensa-based processors offered by Tensilica . With that, Stretch embeds a coarse-grained re-configurable block, termed as Instruction-Set Extension Fabric (ISEF). To alleviate the data bandwidth issues, the ISEF is connected to the base processor and memory via 128-bit wide register ports. The register file dedicated for the ISEF is itself organized as 32 128-bit wide registers, whereas the base processor is aided with a separate 32-bit wide register file.
An instruction scheduling algorithm for MOLEN is implemented in the compiler . Another interesting work in this context is to allocate the FPGA area among target application kernels, so as to minimize the dynamic re-configuration overhead while maximizing overall speed-up performance . Others Several partially re-configurable processors are designed and presented at [91, 92]. The major contribution of these designs is to come up with a FPGA template tailored for arithmetic operations. The FPGA template can be parameterized for input-output ports of various logic elements, alignment of logic elements in the cluster, number of routing channels and segmentation for the interconnects etc.