Logic testing and design for testability by Hideo Fujiwara

By Hideo Fujiwara

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Gn are determined so as to propagate the fault signal along this path to the primary output of the circuit. 4. All inputs to Gj except an input on th e path are set to I for an AND/NAND gate and 0 for an OR/NOR gate. In this figure, the symbol 0/1 represents a signal that has value 0 in the normal or good circuit and I in the faulty circuit, and 1/0 represents a symbol that has value 1 in the normal circuit and 0 in the faulty circuit. This process is called the forward-trace or errorpropagation phase of the method.

Thus, the D-cube speci fies an input condition to propagate an error signal on line I through the gate to line 3. Propagation D-cubes for multiple input errors can be obtained similarly. 11. When both lines 1 and 2 have value 1 in the normal circuit and 0 in the faulty circuit, output line 3 will take 1 in the normal circuit and a in the faulty circuit. Thus, the pr opagati on Dcube becomes 1 2 3 D D D This D-cube can be obtained by intersecting the cubes 111 and OOO,just as is done for single-error propagation D-cubes.

As seen in this example, by assigning uniquely determined values we can avoid the unnecessary choice . 25(a). Supposing that the D-frontier consists of a single gate, we often have specific paths such that every path from the site of the D-frontier to a primary output always goes through those paths. In this example, every path from gate G2 to a primary output passes through the paths F-R and K-M. In order to propagate the value D or D to a primary output, we have to propagate the faulty signal along both F-R and K-M.

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