Memory Controllers for Mixed-Time-Criticality Systems: by Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees

By Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens

This ebook discusses the layout and function research of SDRAM controllers that cater to either real-time and best-effort functions, i.e. mixed-time-criticality reminiscence controllers. The authors describe the state-of-the-art, after which concentrate on an structure template for reconfigurable reminiscence controllers that addresses successfully the fast evolving set of SDRAM criteria, when it comes to worst-case timing and gear research, in addition to implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA improvement board are used as an evidence of proposal of the structure template.

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4 Performance The evaluation of the success or failure of an application can be qualitative, but for the most part it is quantified in terms of performance. Performance is an umbrella term describing the rate at which something of interest is produced or consumed, or the amount of time it takes to complete a specific operation [24]. Each instance of such rate or quantity of time is called a performance metric. For example, a video decoder’s performance may be expressed as frames per second, or a control loop can process a specific number of input samples per millisecond.

They are built according to the philosophy that mechanisms that positively impact the average performance are considered worthwhile, even if they negatively affect the worst case. They exploit knowledge that is only available at run-time to make 10 1 Introduction request-level or command-level scheduling decisions. As a result, they typically provide no useful analytical bounds on performance. 3. , balancing the needs of real-time and best-effort applications. Ideally, these controllers guarantee sufficient performance to satisfy the worst-case performance requirements of the real-time applications, while maximizing the average-case performance for the best-effort applications.

The memory patterns we generate in Chap. 3 are stored within this controller. The analysis from Chap. 4 and the trade-offs we describe in Chap. 5 apply to memory controllers that follows the architecture template we describe here, and the conservative open-page policy in Chap. 6 is implemented on a slightly modified version of the same template. The embedded reconfiguration hardware enables the controller to adapt to different use-cases as we describe in Chap. 7. In Sect. 4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate (LR) server abstraction.

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