By Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
This publication covers structure layout and format migration methodologies for optimizing multi-net twine constructions in complicated VLSI interconnects. Scaling-dependent types for interconnect energy, interconnect hold up and crosstalk noise are lined intensive, and several other layout optimization difficulties are addressed, corresponding to minimization of interconnect strength less than hold up constraints, or layout for minimum hold up in cord bundles inside of a given routing zone. A convenient reference or a advisor for layout methodologies and structure automation ideas, this e-book offers a beginning for actual layout demanding situations of interconnect in complicated built-in circuits.
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Additional resources for Multi-Net Optimization of VLSI Interconnect
Since the voltages of these wires are unknown, and are typically uncorrelated, it makes sense to assume a full, grounded metal plane for calculating the interlayer capacitances above and below the center wire. In contrast, the intralayer, cross-capacitances to adjacent wires at the middle layer in Fig. 9, are connected between the center wire and the two specific neighbor signals on its two sides. The charging and discharging of these capacitance depends on the individual behavior of the two neighbor signals, and not only on the signal at the center wire.
14 Delay uncertainty as a function of wire length for a weak victim Fig. 15 Delay uncertainty versus wire length for a fixed-stage delay Chapter 4 Frameworks for Interconnect Optimization The electrical interconnections in a VLSI system are represented by the geometrical layout of metal layers in a chip. This layout is the result of a complex engineering process, which often involves manual design and automatic layout generation tools, as outlined in Chap. 2. In typical design scenarios, the generated interconnect layout needs to be revised and refined by several iterative steps of checking and optimization.
It is very important to note that although it helps to cope with wire resistance, nonuniform scaling of wires causes the cross-capacitance to grow more than all other capacitances. The ramifications of large cross-capacitance will be covered in the following chapters. In the above model, a fixed resistivity of the metal was assumed, and it was argued that replacing aluminum with copper would improve the situation for a couple of generations. It must be noted, however, that the effective specific resistivity of nanowires will not remain fixed with copper metallization, but will actually get worse with scaling.